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4:1 10-bit 1.2 gsps muxdac evaluation kit - tsev86101g2b ............... ................ ................. ................ ................. ............. user guide
muxdac evaluation kit - tsev86101g2b user guide i 2194b?bdc?04/04 table of contents section 1 introduction ................ ................ ................. ................ ................. ......... 1-1 1.1 description ................................................................................................1-1 1.2 muxdac evaluation kit............................................................................1-1 section 2 general description ............ .............. ............... .............. .............. ......... 2-1 2.1 muxdac evaluation system....................................................................2-1 2.2 block diagram...........................................................................................2-1 2.3 hardware ..................................................................................................2-2 2.3.1 board mechanical characteristics ......................................................2-3 2.3.2 board layout information ...................................................................2-4 2.4 software ....................................................................................................2-5 section 3 getting started........... ................ ................. ................ ................. ......... 3-1 3.1 software installation..................................................................................3-1 3.1.1 platform requirements.......................................................................3-1 3.1.2 installation procedure.........................................................................3-1 3.2 hardware setup ........................................................................................3-8 3.2.1 power supply requirements ..............................................................3-8 3.2.2 hf clock.............................................................................................3-8 3.2.3 analog output.....................................................................................3-8 3.2.4 option selections ...............................................................................3-9 3.2.5 startup procedure (stand-alone mode)............................................3-10 3.2.6 startup procedure (pc driven mode)...............................................3-10 3.2.7 diode temperature monitoring.........................................................3-10 3.2.8 frequency fcw .................................................................................3-11 3.2.9 troubleshooting................................................................................3-11 section 4 operating modes ......... ................. ................ ................. .............. ......... 4-1 4.1 overview ...................................................................................................4-1 4.2 pattern management ................................................................................4-2 4.2.1 typical operation flow.......................................................................4-2 4.3 error messages.........................................................................................4-4
table of contents ii muxdac evaluation kit - tsev86101g2b user guide 2194b?bdc?04/04 section 5 ordering information.............. .............. .............. .............. .............. ....... 5-1 section 6 appendix i: pattern formats .... ................ ................. ................ ............ 6-1 6.1 pattern structure .......................................................................................6-1 6.2 vector structure ........................................................................................6-1 6.2.1 first example......................................................................................6-1 6.2.2 second example ................................................................................6-2 6.3 patterns furnished on the cd-rom .........................................................6-2 section 7 appendix ii: pattern generator software..... ................ ................. ................ ............ 7-1
muxdac evaluation kit - tsev86101g2b user guide 1-1 rev. 2194b?bdc?04/04 section 1 introduction 1.1 description the tsev86101g2b evaluation board (eb) is a prototype board which has been designed in order to facilitate the evaluation and characterization of the ts86101g2b muxdac device (ci-cga-255 cavity up packaged device) over an output band of inter- est of up to 300 mhz, at 600 msps maximum conversion rate (sampling rate limited by the fpga performance only). the tsev86101g2b evaluation kit contains all the softwa re and hardware necessary to setup the board and perform its characterization. the evaluation system of the ts86101g2b muxdac device consists in a configurable printed circuit board (the evaluation board itself), including the soldered muxdac device (ci-cga-255 package), an fpga chip, a serial interface to a windows95 ? or windows98 ? computer and a user interface running on that platform. 1.2 muxdac evaluation kit the muxdac evaluation kit contains: ? 1 muxdac evaluation board ? 1 cd-rom that contains the user interface installation software, the user manual, the pattern generator software, and some pattern files.
muxdac evaluation kit - tsev86101g2b user guide 2-1 rev. 2194b?bdc?04/04 section 2 general description 2.1 muxdac evaluation system the muxdac evaluation system consists of: ? a configurable printed circuit board, including a soldered muxdac in a ci-cga 255 package ? an fpga ? a serial interface to a computer running windows ? 95/98 ? a user interface running on the above platform 500 x 40-bit max test patterns are loaded into the fpga and applied to the muxdac. 2.2 block diagram figure 2-1. block diagram control signal onboard connection to pc (labview tm ...) fpga with integrated sram 80-bit differential data bus 10-bit mux dac muxdac data clock differential lvds dsp clock differential input clock spectrum analyzer analog differential output
general description 2-2 muxdac evaluation kit - tsev86101g2b user guide 2194b?bdc?04/04 2.3 hardware figure 2-2. muxdac printed board circuit figure 2-2 show, from left to right: serial interface connector, fpga surrounded with ter- mination resistors and 50 ? tracks, muxdac area, sampli ng delay rotating switch, sma connectors for differential clock and output. from top to bottom: fpga glue logic (status leds, reset button, serial interface crystal, configuration eprom), muxdac power connectors (4 mm plugs), fpga and mux- dac, clock interface (delay line with 2 programming switches, differential to single ended interface), fpga power connectors (4 mms plugs).
general description muxdac evaluation kit - tsev86101g2b user guide 2-3 2194b?bdc?04/04 2.3.1 board mechanical characteristics 2.3.1.1 board layer thickness profile the board layer numbers, thickness and functions are given below, from top to bottom. the tsev86101g2b evalua tion board is a ni neteen layer pc b board made of 10 cop- per layers and 9 dielectric layers. the metal layers correspond respectively from top to bottom to stages of two ac signal trace planes (muxdac or fpga) with one ground plane (a gnd /d gnd ) in between. the metal layers are isolated from one to another by htg epoxy layers. dielectric layer thickness: ? between layers 1 and 2, 9 and 10: 200 m ? 350 m for all other layers dielectric constant: r = 4.1 at 1 mhz insertion loss: -0.01 db/inch at 1 mhz the previously described mechanical an d frequency characteristics make the board particularly suitable for device evaluation and characterization in the high frequency domain and in a wide temperature range. table 2-1. board layer thickness profile layer characteristics layer 1 copper layer copper thickness = 35 m ac signal traces = 50 ? microstrip lines dc signal traces (diode, cs) layer 2 copper layer copper thickness = 35 m a gnd , d gnd (separate traces) layer 3 copper layer copper thickness = 35 m ac signal traces = 50 ? microstrip lines (input data) layer 4 copper layer copper thickness = 35 m a gnd , d gnd (separate traces) layer 5 copper layer copper thickness = 35 m muxdac v cc , fpga +1.5v supply layer 6 copper layer copper thickness = 35 m separate v eea and v eed fpga +2.5v and +3.3v supplies layer 7 copper layer copper thickness = 35 m a gnd , d gnd (separate traces) layer 8 copper layer copper thickness = 35 m ac signal traces = fpga signals layer 9 copper layer copper thickness = 35 m a gnd , d gnd (separate traces) layer 10 copper layer copper thickness = 35 m ac signal traces = 50 ? microstrip lines (muxdac input data)
general description 2-4 muxdac evaluation kit - tsev86101g2b user guide 2194b?bdc?04/04 2.3.1.2 input accesses the board inputs (which correspond to th e fpga inputs) are accessed via an rs-232 serial port (9 points pin to pin connector with the rx and tx pins not inversed). the clock input is accessed via sma connector. 2.3.1.3 output accesses the board outputs are accessed differentially via sma connectors. 2.3.1.4 power supplies and ground accesses the muxdac power supplies (v eed , v eea , v cc ) are accessed via banana jacks (4 mm plugs). the fpga power supplies (+1.5v, +2.5v, +3.3v) are accessed via banana jacks (4 mm plugs). 2.3.1.5 function setting accesses the diode function for die junction temp erature monitoring is accessed via a 2 mm banana jack. the cs (shift select for dsp clock) function is accessed through a coding wheel. 2.3.2 board layout information in order to evaluate the ts86101g2b muxdac device easily and efficiently, two options were explored. the first one required the use of a pattern generator, which could be a costly solution for many users. the second option was to use an fpga, which would provide specified patterns to the muxdac, as well as the muxdac input clock. although the later option would limit the speed range of the evaluation (the maximum frequency attainable at the output of the muxdac, namely 600 msps, is limited by both the fpga output frequency ca pabilities and the memory width s), it was preferred to the former option because it provided a more flexible way to characterize the muxdac device. because of the use of an fpga, additional care had to be taken with the board layout, in order to separate effectively the muxdac sign al traces from the fp ga signal traces as well as the ground traces. the following puts forward the board layout recommendations and demonstrates how the evaluation board fulfills the many implementation constraints. 2.3.2.1 digital inputs/analog outputs the board uses 50 ? impedance microstrip lines for the digital data and clock inputs and analog outputs. the input and clock signals are routed on one layer only, without using any through-hole via. the lines connecting the fpga to the muxdac are 50 ? lines. 2.3.2.2 dc function settings the dc signal traces are low impedance. 2.3.2.3 power supplies layers 9 and 11 are dedicated to the mu xdac and fpga power supply traces (v cc , v eed , v eea and +1.5v, +2.5v and +3.3v). the supply traces are routed in order to present low impedance, and are surrounded by ground planes (layers 7 and 13). the analog and digital negative power supply traces ar e independent, but the possibility exists to short-circuit both supplies on the top metal layer. each incoming power supply is bypassed by a 1 f tantalum capacitor in parallel with a 10 nf chip capacitor. each power supply access is decoup led by a 10 nf capacitor and a 100 pf surface mounted chip capacitors in parallel, located as close as possible to the device. note: the decoupling capacitors are superimposed . in this configuration, the 100 pf capacitor must be mounted first.
general description muxdac evaluation kit - tsev86101g2b user guide 2-5 2194b?bdc?04/04 2.4 software the muxdac evaluation user interface software is a labview ? compiled graphical interface, that requires no license to run on a windows ? 95/98. figure 2-3. muxdac user interface note: the software uses intuitive buttons and pop-up menus to send data to the mux-dac.
muxdac evaluation kit - tsev86101g2b user guide 3-1 rev. 2194b?bdc?04/04 section 3 getting started 3.1 software installation 3.1.1 platform requirements a pc running windows ? 95/98, with an rs-232 serial port is required. figure 3-1. contents of the installation compact disk 3.1.2 installation procedure the installation is performed in 3 steps: 1. install the muxdac10bit 4-1 v1.0. 2. install the ni labview ? run time engine 6.0. 3. install the ni-visa driver. 3.1.2.1 to install the software on a pc 1. install the muxdac10bit 4-1 v1.0 1.1. insert the cd-rom. 1.2. open an explorer window. 1.3. double-click on d:\installer10bit 4-1\ setup.exe .
getting started 3-2 muxdac evaluation kit - tsev86101g2b user guide 2194b?bdc?04/04 figure 3-2. d:\intaller 10bit 4-1 contents 1.4. a setup window appears (see figure 3- 3) and suggests in stalling the program in c:\program files\muxdac\10bit 4-1: figure 3-3. muxdac 10bit 4-1 v1.0 intallation window 1.5. click on finish to continue the installation.
getting started muxdac evaluation kit - tsev86101g2b user guide 3-3 2194b?bdc?04/04 1.6. a window appears (see figure 3-4) to confirm that the installation is successful. figure 3-4. muxdac installation dialog box a directory named c:\program files\muxdac\10bit 4-1 is created with an executable software (this window does not appe ar when installing the software). figure 3-5. c:\program files\muxdac\10bit 4-1 contents 1.7. the muxdac 10bit 4-1.exe software is automatically added to the startup menu\programs\muxdac 10bit 4-1 (?menu demarrer\programmes? in the french version). a window appears (see figure 3-6) to indicate that muxdac 10bit 4-1 executable file is installed. figure 3-6. muxdac 10bit 4-1.exe software 2. installation of ni labview ? run time engine 6.0 if labview ? is not installed on your pc, it is necessary to install this free ni labview ? software.
getting started 3-4 muxdac evaluation kit - tsev86101g2b user guide 2194b?bdc?04/04 2.1. when the first step has been successfully completed, a window appears (see figure 3-7). install run time labview engine 6.0. figure 3-7. 1 st labview run-time engine setup window 2.2. click on next to continue the installation. a window appears (see figure 3-8) and suggests installing the program in c:\program files\national instruments\ figure 3-8. 2 nd labview run-time engine setup window
getting started muxdac evaluation kit - tsev86101g2b user guide 3-5 2194b?bdc?04/04 2.3. click on next to continue the installation. w hen the installation is finished, figure 3-9 appears. figure 3-9. 3 rd labview run-time engine setup window 2.4. click on finish to terminate the installation. 3. installation of ni-visa software if labview ? is not installed on your pc, it is necessary to install this free ni labview ? software. 3.1. double-click on d:\insta ller10bit 4-1\ni-visa2.5.2\ setup.exe . 3.2. figure 3-10 appears. click next to continue th e installation.
getting started 3-6 muxdac evaluation kit - tsev86101g2b user guide 2194b?bdc?04/04 figure 3-10. 1 st ni-visa setup window 3.3. when the installation is fini shed, figure 3-11 appears. click on finish . figure 3-11. 2 nd ni-visa setup window
getting started muxdac evaluation kit - tsev86101g2b user guide 3-7 2194b?bdc?04/04 3.4. figure 3-12 appears and ask you to restart your computer. click on ye s to restart your computer. figure 3-12. ni-visa installer dialog box 3.1.2.2 installation testing 1. select the program muxdac 10bit 4-1 v1.0 from the startup/program menu or double-click on c:\program files\muxdac\10bit 4-1\muxdac 10bit 4-1.exe. 2. figure 3-13 will be displayed. there must be no error message and the error display must not be highlighted. if an error is detected, the error display is highlighted: simply click on quit , and close the muxdac window. figure 3-13. muxdac user interface 3.1.2.3 troubleshooting 1. check that the c:\ hard disk is properly mounted. 2. check that you have the right to write in the directory. 3. check for available disk space. 4. check that the serial com port is free and properly configured. 5. check that the serial com port is exactly declared with c:\program files\mux- dac\10bit 4-1\muxdac 10bit 4-1.ini file.
getting started 3-8 muxdac evaluation kit - tsev86101g2b user guide 2194b?bdc?04/04 3.2 hardware setup 3.2.1 power supply requirements 3.2.1.1 fpga ? core: 2.5v +10/-5% (keep core voltage as high as possible for higher speed and assume current of 1a at 1 ghz) ? periphery: 3.3v 5% ? d gnd : 0v reference voltage the core and periphery supplies should be switched on at the same moment. 3.2.1.2 termination voltage 1.2v ? 1.6a typ., 1.5v max (2a) 3.2.1.3 muxdac see specifications on section 2. ? v eea : analog ecl voltage, -5.0v (0.4 to 0.6a) ? v eed : digital ecl voltage, -5.0v ? v ccd : digital pecl voltage, +5.0v ? a gnd : 0v reference analog voltage ? d gnd : 0v reference digital voltage v eea , v eed and v ccd supplies should be switched on at the same moment (otherwise, if this is not possible, in the following order: v ccd , v eea then v eed ). a gnd and d gnd should be connected together. 3.2.2 hf clock use the hf generator with a 50 ? output. 100 to 600 mhz, -1 at +5 dbm 3.2.3 analog output use an oscilloscope and/or a spectrum analyzer with a 50 ? input.
getting started muxdac evaluation kit - tsev86101g2b user guide 3-9 2194b?bdc?04/04 3.2.4 option selections figure 3-14. hardware descripton ? s1: fpga reset push button ? d2: orange led, indicating fpga initialization phase ? d3: red led, indicating fpga initialization errors ? u11: muxdac digital inputs delay setting (hexadecimal coding) ? j10/opt1: fpga standalone setting (with jumper: ramp output, else zero output) ? j10/opt2, 3, 4: reserved. jumper must be plugged in do not use: ? jp1: jtag programming mode when jumper is unplugged. used only for fpga debugging. the jumper must be plugged in for normal operation. ? j9: 12-pin jtag connector. used only for fpga debugging.
getting started 3-10 muxdac evaluation kit - tsev86101g2b user guide 2194b?bdc?04/04 3.2.5 startup procedure (stand-alone mode) the hf clock should be on to provide the fcw clock to muxdac through the j13 sma connector. the muxdac should be started first: v eea , v eed and v ccd supplies should be switched on at the same moment. jumper opt1 may be unplugged (no jumper on opt1). when the muxdac is ready, fpga can be powered on. the core 2.5v and periphery 3.3v supplies should be switched on at the same moment, the terminal voltage 1.2v must be the last fpga supply to stabilize in order to properly activate the power-on- reset circuit, and start initialization. the orange led lights during the eprom download phase, then turns off. no led must light afte r initialization. after startup, it is recommended to reset the fpga, to lock the internal pll on a stable clock. it?s only after reset that the opt1 jumper may be plugged in to switch to the default (ramp) pattern. 3.2.6 startup procedure (pc driven mode) the hf clock should be on to provide the fcw clock to muxdac through the j13 sma connector. muxdac should be started first: v eea , v eed and v ccd supplies should be switched on at the same moment. the startup option must be set to the zero mode for a clean startup of the muxdac (no jumper on opt1). when the muxdac is ready, fpga can be powered on. the core 2.5v and periphery 3.3v supplies should be switched on at the same moment, the terminal voltage 1.2v must be the last fpga supply to stabilize in order to properly activate the power-on- reset circuit, and start initialization. the orange led lights during the eprom download phase, then turns off. no led must light afte r initialization. after startup, it is recommended to reset the fpga, to lock the internal pll on a stable clock. when the fpga is ready,run the muxdac 10bit 4-1.exe software. 3.2.7 diode temperature monitoring the diode pad temp is provided for die junction temperature monitoring. figure 3-15. diode temperature monitoring from muxdac v d18 d17 d20 d19 2 mm red connector under evaluation board d13 d12 d11 d16 d15 d14
getting started muxdac evaluation kit - tsev86101g2b user guide 3-11 2194b?bdc?04/04 for a given forced current in pad temp, the voltage across the diode mounted transistor depends linearly on the temperature. since the characteristic of the diode may vary from deviate device, the voltage across the diode must first be measured for a known junction temperature. the measured diode mounted transistor, vbe, values as a function of junction tempera- ture at i = 1 ma are given below. figure 3-16. junction temperature monitoring 3.2.8 frequency fcw the frequency of hf clock can be changed without turning off the board and muxdac. but it is recommended that the fpga be reset in order to lock the internal pll on a sta- ble clock. during reset, opt1 jumper may be unplugged. 3.2.9 troubleshooting 3.2.9.1 orange led remains alive ? jumper jp1 is not plugged (fpga in jtag mode): plug in a jumper ? bad pll lock: power off the muxdac, and restart fpga ? power problem (bad 3.3v rise time): check 2.5 and 3.3v voltage ? restart the 3.3v power supply, unplug and replug the 3.3v connector or, change the 3.3v power supply 3.2.9.2 red led remains alive ? same as the orange led ? check if an eprom is properly plugged in the u4 socket 1.8 0 10 20 30 40 50 60 70 80 90 100 110 120 1.9 2.0 2.1 2.2 2.3 2.4 2.5 2.6 vdiode versus t j (at i = 1 ma) vdiode (v) t j ( c)
getting started 3-12 muxdac evaluation kit - tsev86101g2b user guide 2194b?bdc?04/04 3.2.9.3 1.2v supply overloaded ? weak power supply: 1.7a typ required ? bad pll lock: power off the muxdac, and restart fpga ? check for possible shorts 3.2.9.4 2.5v supply overloaded ? weak power supply: 1a typ required ? check for possible shorts 3.2.9.5 muxdac supplies overloaded ? check for possible shorts (beware of smt components below socket) 3.2.9.6 permanent com errors ? reset fpga, reset software (reset button) ? exit and restart the software ? verify that muxdac board is connected to com1 ? verify that com1 is configured properly (even parity, 1 stop bit, lsb first, 9600 baud, rts, dtr signals) ? test fpga initialization (leds, clocks, muxdac signals) ? reset fpga and check muxdac signals, muxdac clock (opt1 maybe unplugged) ? the rs-232 serial interface should no t have the rx and tx pins inversed. 3.2.9.7 muxdac to fpga clock problems ? check for possible shorts (beware of conflicts between the delay line and the muxdac) ? check inputs and outputs from the differential to the single ended converter ? check the high frequency clock connections (j13 sma) and settings (frequency, level) ? check fpga initialization (pll locked) note: when restarting the user interface software, always reset the fpga before sending a pattern.
muxdac evaluation kit - tsev86101g2b user guide 4-1 rev. 2194b?bdc?04/04 section 4 operating modes 4.1 overview the muxdac is intended to feed a device under test with predefined patterns, stored on the host computer, in order to observe and measure most converter performances. the evaluation system is build around an fpga, providing an internal pattern capacity of 20 kwords ram, organized as 512 40-bi t rows. once loaded into the fpga memory, test patterns are looped back indefinitely, under software control. four 10-bit words are applied to the device under test, using differential signaling every rising edge of the fpga fast clock. in order to ease synchronization, the differential clock for pattern sam- pling is regenerated within the fpga and propagated to the muxdac. the software provides a graphical user interface to configure the fpga pattern genera- tors, store test vectors in the board memory, and control execution. buttons and pop-up menus allow the user to easily perform: ? pattern file selection ? pattern memory downloading into the board pattern memory the computer interface uses a standard asyn chronous serial port. the serial port is organized as a byte oriented data flow running at 9600 baud, even parity, single stop bit, positive logic signaling, lsb first. the transfer protocol makes use of the dtr and rts lines for synchronization. the automatic configuration provides users with simple access to basic operations (pat- tern initialization, pattern start and stop) without any knowledge about the board or the software?s internal structure.
operating modes 4-2 muxdac evaluation kit - tsev86101g2b user guide 2194b?bdc?04/04 4.2 pattern management test pattern generation and test pattern format are detailed in section 6 and section 7. writing patterns to the board?s ram memory is transparently handled by the user inter- face software (length computing, register programming, byte formatting, serial link framing), as long as the pattern format is respected. 4.2.1 typical operation flow 1. insert the muxdac in the socket if the mux-dac is not soldered ( be careful of pin 1). 2. apply the hf clock to the board. 3. power on the muxdac. 4. power on the fpga. 5. connect appropriate test tools to the analog output (oscilloscope, spectrum ana- lyzer, etc...). 6. start the user interface software. figure 4-1. muxdac user interface 7. reset the fpga. 8. check that no error is flagged. 9. select a pattern. figure 4-2. pattern selection
operating modes muxdac evaluation kit - tsev86101g2b user guide 4-3 2194b?bdc?04/04 9.1. click on in the user inte rface pattern file menu. the select pattern file window pops-up. 9.2. select a pattern file by double-click on the file name. the file name is now dis- played in the pattern file box. the nb vectors and header box indicate information about the pattern file. figure 4-3. muxdac user interface 9.3. click on send pattern . wait until end of transfer file. 10. start the pattern operation by clicking on start or press f4 on the keyboard. 11. stop the pattern operation by clicking on stop or press f5 on the keyboard. by default, the path used to select a pattern file is the one defined in: c:\program files\muxdac\10bit 4-1\muxdac 10bit 4-1.ini this default path can be changed by modifying the item patterndir of the file muxdac 10bit 4-1.ini by default, there is a single pattern file which is: c:\program files\muxdac\10bit 4-1\600m_264.9m_0.0dbfs.txt
operating modes 4-4 muxdac evaluation kit - tsev86101g2b user guide 2194b?bdc?04/04 4.3 error messages figure 4-4. communication problem dialog box ? check that the evaluation board is powered on. ? check the serial interface cable. ? check serial port settings (even parity, 1 stop bit, lsb first, 9600 baud, rts, dtr signals). ? reset or reinitialize fpga (power off 2.5 and 3.3v supplies). ? check the test pattern file format (if the pattern was modified manually).
muxdac evaluation kit - tsev86101g2b user guide 5-1 rev. 2194b?bdc?04/04 section 5 ordering information part number package temperature range screening level comments tsx86101g2bgl cbga 255 ambient prototype please contact your local atmel sales office ts86101g2bcgl cbga 255 commercial grade 0 c < tc tj < 90 c standard TS86101G2BVGL cbga 255 industrial grade -40 c < tc tj < 110 c standard
muxdac evaluation kit - tsev86101g2b user guide 6-1 rev. 2194b?bdc?04/04 section 6 appendix i: pattern formats the pattern file must be written in a fixed format: ? plain text file ? 512 pattern lines maximum (board maximum allowed value) 6.1 pattern structure as the multiplexing ratio is not a power of 2, care should be exercised to ensure a clean transition when looping back from the last vector line to the first one: for p 4x10-bit samples per analog signal period sequences, it is recommended that the pattern contains 4 x p words (=> p-1 length integer value). the pixel clock should thus be selected such that p 512. the minimum pattern size has been fixed to 4 vectors. should the pattern be shorter than 4 vectors, then it must be simply repeated in order to fill at least the requested 4 vectors. the maximum pattern size is 512 lines, which is the maximum memory depth in the fpga. 6.2 vector structure vector 0: 1000000000 1000000001 1000000010 1000000011 bits vector: a9............a0 b9............b0 c9............c0 d9............d0 use the binary code for pattern bits. 6.2.1 first example default pattern (?ramp?, 4 first lines from pr file) file pr.dat clock: 600 mhz frequency: 10 mhz vecteur 0: 0000000001 0000000010 0000000011 0000000100 vecteur 1: 0000000101 0000000110 0000000111 0000001000 vecteur 2: 0000001001 0000001010 0000001011 0000001100 vecteur 3: 0000001101 0000001110 0000001111 0000010000 etc... note: there is no specific structure for the header. all lines preceding the line begin- ning by vecteur 0: are ignored.
appendix i: pattern formats 6-2 muxdac evaluation kit - tsev86101g2b user guide 2194b?bdc?04/04 6.2.2 second example fc: 600 mhz fout: 110.1 mhz level: 0 dbfs vecteur 0: 1000000000 1111010011 1101111011 0101100000 vecteur 1: 0000000010 0100000010 1100101111 1111110100 vecteur 2: 1001100110 0001011110 0001000111 1000111011 vecteur 3: 1111101000 1101010001 0100101000 0000000000 etc? this example has the format used by the pattern generator software furnished with the mux-dac (see section 7). the header displays the clock rate (600 mhz), the frequency fout of the sinewave to be generated (110.1 mhz) and the amplitude of the sinewave (0 dbfs). 6.3 patterns furnished on the cd-rom different patterns are furnished on the cd-rom. the structure used is the following one: directory: 600m_0.0dbfs files: 600m_15.3m_0.0dbfs.txt 600m_264.9m_0.0dbfs.txt 600m_299.1m_0.0dbfs.txt etc... in the above example: ? the name of the directory indicates that fclock = 600 mhz and the sinewave generated is full scale (0 dbfs). ? the files of this directory indicate first the clock rate (600m) then the fout frequency (15.3m) and then the output level (0.0 dbfs). ? all this information is written in the header of the pattern file. note: patterns furnished are at a clock rate of 600 msps. all these pattern files can be used with other sampling rates. when changing the sampling rate by a factor k, the fout frequency is modified by the same factor k and the output level remains unchanged. if the wanted pattern is not available on the cd-rom, it is possible to generate other patterns with the software furnished (see section 7).
muxdac evaluation kit - tsev86101g2b user guide 7-1 rev. 2194b?bdc?04/04 section 7 appendix ii: pattern generator software a pattern generator software is furnished on the cd-rom. the name of the executable is muxdac10b.exe it is first necessary to copy this executable file (d:\patterns\pattern generator soft- ware\muxdac10b.exe) on your hard disk. run this software by double-clicking on muxdac10b.exe a window appears (see figure 7-1). figure 7-1. pattern generator user interface 1. enter the output level (in dbfs) of the sine wave to be generated. note: in single ended: 0 dbfs = full scale = 1 vpp = 0.5v peak = -6 dbv = +4 dbm in differential: 0 dbfs = full scale = 2 vpp = 1v peak = 0 dbv = +10 dbm 2. enter the output frequency (in mhz). figure 7-2. pattern generator user interface
appendix ii: pattern generator software 7-2 muxdac evaluation kit - tsev86101g2b user guide 2194b?bdc?04/04 3. enter the clock rate (in mhz). figure 7-3. pattern generator user interface figure 7-4. pattern generator user interface the software calculates the numb er of cycles nbsample x fout/fs. in the above example nbsample = 4 x 500, fout = 10 and fs = 600 so that the num- ber of cycles is 33.3333.... the number of cycles must be an odd integer so that is truncated to 33. the new fout value is also fout = 33 x fs/nbsample = 9.9 mhz when the pattern is generated, figure 7-4 disappears. two files are generated in the current directory: ? volt_file.txt: this is the voltage values associated to each word of the pattern file. ? pattern_file.txt: this is the pattern file containing 500 vectors of 4 words of 10 bits. it is recommended to rename this file in order to avoid overwriting it when generating another pattern file. to rename the file pattern_file.txt we recommend the following structure: __.txt in the above example, the file name would be 600m_9.9m_0.0dbfs.txt
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